Oʻzbekcha
BUL ALGEBRASI QONUNLARI
Jurnal
Pedagogik ta’lim va tarbiya transformatsiyasida fundamental, amaliy va innovatsion tadqiqotlarning konseptual asoslari
Nashr
Pedagogik ta’lim va tarbiya transformatsiyasida fundamental, amaliy va innovatsion tadqiqotlarning konseptual asoslari xalqaro ilmiy-amaliy anjuman (2026-yil, 23-iyun)
Annotatsiya
Ushbu maqolada Boolean algebrasi va De Morgan qonunlari asosida raqamli mantiqiy sxemalarni optimallashtirishga doir yondashuvlar tahlil qilingan. Tadqiqotda murakkab mantiqiy ifodalar De Morgan teoremalari orqali soddalashtirilib, Logisim va Proteus muhitlarida simulyatsiya qilindi. Natijalar sxema elementlarining kamayishi, energiya sarfining pasayishi va kechikish vaqtining qisqarishi bilan tasdiqlandi.
Kalit so‘zlar
Boolean algebra
De Morgan qonunlari
Logisim
NAND
NOR.
Proteus
circuit optimization
digital logic
English
This paper examines the optimization of digital logic circuits using Boolean algebra and the De Morgan laws. Complex logic expressions were simplified using De Morgan’s theorems and implemented in Logisim and Proteus environments. The results demonstrate a reduction in circuit elements, power consumption, and propagation delay time.
Boolean algebra
De Morgan laws
Logisim
NAND
NOR.
Proteus
circuit optimization
digital logic
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